Among various types of flash memory device, NAND-type flash memory devices are increasingly used as a high-capacity data storage media. To meet the demand for the high-capacity memory devices with high-integration, a multi-level cell (MLC) structure for the flash memory devices has recently been proposed, which is capable for increasing the data storage capacity in a smaller chip size. Generally, a single level cell (SLC) includes two states, i.e., a programmed state and an erased state, in one memory cell. Compared to a MLC flash memory device, the MLC flash memory device may store two bits or more in one memory cell. Therefore, the storage capacity of the MLC flash memory device is twice or more than a SLC flash memory device.
FIG. 1 illustrates threshold voltage distributions of programmed and erased states of a 2-bit MLC NAND-type flash memory device. Memory cells of the flash memory device may include erased or programmed states. In a SLC flash memory device, erased memory cells may have at least one relatively low threshold voltage distribution, for example, lower than 0 V. On the contrary, programmed memory cells may have at least one relatively high threshold voltage distribution, for example, higher than 0 V.
In the MLC NAND-type flash memory device where 2-bit data may be programmed in one memory cell, each memory cell may include a threshold voltage distribution 110 corresponding to an erased state (erased threshold voltage distribution) and a plurality of threshold voltage distributions 120, 130 and 140 corresponding to a plurality of programmed states (programmed threshold voltage distribution). The programmed threshold voltage distributions 120, 130 and 140 are distinguished from the erased threshold voltage distribution 110 by a first read voltage Vread0, for example, 0 V. The programmed threshold voltage distributions 120, 130 and 140 are distinguished from each other by a second read voltage Vread1 and a third read voltage Vread2, respectively. As shown in FIG. 1, the programmed threshold voltage distributions 120, 130 and 140 may be separated from each other between the first read voltage Vread0 and a pass voltage Vpass in the MLC NAND flash memory device and each of the threshold voltage distribution 110, 120, 130, 140 may a width as narrow as possible. Further, the threshold voltage distributions must be appropriately controlled such that the erased threshold voltage distribution as well as the programmed threshold voltage distribution has a width as narrow as possible in the case where the flash memory device employs an MLC structure.
A method of erasing data of the MLC flash memory device may include a pre-program operation, a normal erase operation, and a post-program operation. These operations may be performed in sequence. The post-program operation corresponds to a soft program, may be performed after a memory cell is erased and before the memory cell is programmed to various levels. Particularly, the post-program operation may be performed to narrow the width of a threshold voltage distribution that may be broadened after an erase operation. Further, the post-program operation may be performed in an incremental step pulse program (ISPP) method. However, a page by page program operation and a bit by bit verify operation, which are typically used in the ISSP method, are not used, instead a program operation is performed in units of a block. In other words, the post-program operation is performed using a method of programming the memory cell to a desired level by equally applying a program bias lower than a bias used in the program operation to all the word lines of one block at the same time.
During the post-program operation, a program verify operation is also performed after a program pulse is applied. The program operation is terminated only if all the memory cells exceed a verify level. Unlike the program operation, the post-program operation is terminated even if only one cell exceeds the verify level. The program verify operation may be performed by applying 0 V to all the word lines of a corresponding block so that a right tail of the threshold voltage is positioned to −1 V, as illustrated in FIG. 2, to prevent an increase in the width of the threshold voltage distribution due to an interference during the program operations.
FIG. 2 illustrates a shift of a threshold voltage distribution after performing a post-program operation of a NAND-type flash memory device. Reference numeral 210 denotes a threshold voltage distribution of a memory cell after a normal erase operation and reference numeral 212 denotes a threshold voltage distribution of a memory cell after the post-program operation. As the MLC NAND flash memory device requires a higher program voltage than a SLC flash memory device in order to exist a plurality of programmed states. The threshold voltage distribution of the memory cell may be shifted, thereby cause failure due to a program disturb or a program stress.
FIG. 3 illustrates variations of a threshold voltage distribution of a memory cell due to a program disturb or a program stress. Reference numeral 310 denotes a threshold voltage distribution of a memory cell after a post-program operation. As shown, a right tail of the threshold voltage distribution 310 is positioned at −1 V. Reference numerals 312 and 314 denote threshold voltage distributions of the memory cell undergoing a test program operation, e.g., number of partial program (NOP), once and twice, respectively, for confirming how the threshold voltage may be shifted due to the program disturb or the program stress after the post-program operation. As illustrated in FIG. 3, the threshold voltage distribution of the memory cell is shifted to the right when the program disturb or the program stress occurs after the post-program is performed. In particular, when performing the NOP twice, a right tail of the threshold voltage distribution 314 exceeds 0 V, that is, threshold voltages of some memory cells exceed 0 V (see dotted circle of FIG. 3), thus leading to a program fail as if these memory cells are determined as programmed cells in spite of erased cells.
The threshold voltage distribution may be down-shifted to prevent the program fail. The threshold voltage distribution may be shifted toward the left side thereof so that the right tail of the threshold voltage distribution is positioned at a voltage lower than −1 V when the erase operation including the post-program operation is completed in order to prevent the program fail, NOP fail, caused by the shift of the threshold voltage distribution due to the program disturb or the like in some degree. However, a verify level obtainable by applying 0 V to all the word lines during the post-program operation is about −1 V, as illustrated in FIG. 2, a negative bias may not be applied to the word lines. Accordingly, it is difficult to down-shift the threshold voltage distribution obtainable by a typical post-program operation to a level less than about −1 V.